rtlpy.design.types.AccessType

class rtlpy.design.types.AccessType(value, names=None, *values, module=None, qualname=None, type=None, start=1, boundary=None)

Bases: Enum

Type to represent Memory Access-Types

__init__(*args, **kwds)

Methods

from_string(label)
is_readable(access)	Returns true if the access type is considered "readable".
is_writable(access)	Returns true if the access type is considered "writable".

Attributes

READ_ONLY	no effect
READ_WRITE	no effect
READ_CLEARS	clears all bits
READ_SETS	sets all bits
WRITE_READ_CLEARS	clears all bits
WRITE_READ_SETS	sets all bits
WRITE_CLEARS	no effect
WRITE_SETS	no effect
WRITE_SETS_READ_CLEARS	clears all bits
WRITE_CLEARS_READ_SETS	sets all bits
WRITE_ONE_CLEARS	no effect
WRITE_ONE_SETS	no effect
WRITE_ONE_TOGGLES	no effect
WRITE_ZERO_CLEARS	no effect
WRITE_ZERO_SETS	no effect
WRITE_ZERO_TOGGLES	no effect
WRITE_ONE_SETS_READ_CLEARS	clears all bits
WRITE_ONE_CLEARS_READ_SETS	sets all bits
WRITE_ZERO_SETS_READ_CLEARS	clears all bits
WRITE_ZERO_CLEARS_READ_SETS	sets all bits
WRITE_ONLY	error
WRITE_ONLY_CLEARS	error
WRITE_ONLY_SETS	error
WRITE_ONE	no effect
WRITE_ONLY_ONE	error

READ_CLEARS = 'RC'

clears all bits

– SRAM Implementation: input latch set signal, output value signal

Type:

W

Type:

no effect, R

READ_ONLY = 'RO'

no effect

– SRAM Implementation: input value signal

Type:

W

Type:

no effect, R

READ_SETS = 'RS'

sets all bits

– SRAM Implementation: input latch clear signal, output value signal

Type:

W

Type:

no effect, R

READ_WRITE = 'RW'

no effect

– SRAM Implementation: output value signal

Type:

W

Type:

as-is, R

WRITE_CLEARS = 'WC'

no effect

– SRAM Implementation: input latch set signal, output value signal

Type:

W

Type:

clears all bits, R

WRITE_CLEARS_READ_SETS = 'WCRS'

sets all bits

– SRAM Implementation: output value signal

Type:

W

Type:

clears all bits, R

WRITE_ONE = 'W1'

no effect

– SRAM Implementation: output value signal

Type:

W

Type:

first one after HARD reset is as-is, other W have no effects, R

WRITE_ONE_CLEARS = 'W1C'

no effect

– SRAM Implementation: input latch set signal, output value signal

Type:

W

Type:

1/0 clears/no effect on matching bit, R

WRITE_ONE_CLEARS_READ_SETS = 'W1CRS'

sets all bits

– SRAM Implementation: output value signal

Type:

W

Type:

1/0 clears/no effect on matching bit, R

WRITE_ONE_SETS = 'W1S'

no effect

– SRAM Implementation: input latch clear signal, output value signal

Type:

W

Type:

1/0 sets/no effect on matching bit, R

WRITE_ONE_SETS_READ_CLEARS = 'W1SRC'

clears all bits

– SRAM Implementation: output value signal

Type:

W

Type:

1/0 sets/no effect on matching bit, R

WRITE_ONE_TOGGLES = 'W1T'

no effect

– SRAM Implementation: output value signal

Type:

W

Type:

1/0 toggles/no effect on matching bit, R

WRITE_ONLY = 'WO'

error

– SRAM Implementation: output value signal

Type:

W

Type:

as-is, R

WRITE_ONLY_CLEARS = 'WOC'

error

– SRAM Implementation: input latch set signal, output value signal

Type:

W

Type:

clears all bits, R

WRITE_ONLY_ONE = 'WO1'

error

– SRAM Implementation: output value signal

Type:

W

Type:

first one after HARD reset is as-is, other W have no effects, R

WRITE_ONLY_SETS = 'WOS'

error

– SRAM Implementation: input latch clear signal, output value signal

Type:

W

Type:

sets all bits, R

WRITE_READ_CLEARS = 'WRC'

clears all bits

– SRAM Implementation: output value signal

Type:

W

Type:

as-is, R

WRITE_READ_SETS = 'WRS'

sets all bits

– SRAM Implementation: output value signal

Type:

W

Type:

as-is, R

WRITE_SETS = 'WS'

no effect

– SRAM Implementation: input latch clear signal, output value signal

Type:

W

Type:

sets all bits, R

WRITE_SETS_READ_CLEARS = 'WSRC'

clears all bits

– SRAM Implementation: output value signal

Type:

W

Type:

sets all bits, R

WRITE_ZERO_CLEARS = 'W0C'

no effect

– SRAM Implementation: input latch set signal, output value signal

Type:

W

Type:

1/0 no effect on/clears matching bit, R

WRITE_ZERO_CLEARS_READ_SETS = 'W0CRS'

sets all bits

– SRAM Implementation: output value signal

Type:

W

Type:

1/0 no effect on/clears matching bit, R

WRITE_ZERO_SETS = 'W0S'

no effect

– SRAM Implementation: input latch clear signal, output value signal

Type:

W

Type:

1/0 no effect on/sets matching bit, R

WRITE_ZERO_SETS_READ_CLEARS = 'W0SRC'

clears all bits

– SRAM Implementation: output value signal

Type:

W

Type:

1/0 no effect on/sets matching bit, R

WRITE_ZERO_TOGGLES = 'W0T'

no effect

– SRAM Implementation: output value signal

Type:

W

Type:

1/0 no effect on/toggles matching bit, R

classmethod is_readable(access: AccessType) → bool

Returns true if the access type is considered “readable”. An access type is considered “readable” iff a read transaction does not result in an error

Parameters:

access (AccessType) – The access type to check

Returns:

True if readable, else false

Return type:

bool

classmethod is_writable(access: AccessType) → bool

Returns true if the access type is considered “writable”. An access type is considered “writable” iff a write transaction has an impact on state

Parameters:

accces (AccessType) – The access type to check

Returns:

True if writable, else False

Return type:

bool